In a computer system, memory access is one of the most vital, yet time consuming operations the CPU (Central Processing Unit) must perform to accomplish its functions. As a result, many memory access schemes have been developed along with improvements in memory device technology to shorten memory access time.
Data access time problems also exist in accessing static memory structures such as a queue or FIFO (first in, first out). When the FIFO is not empty and contains data, an actual memory access is performed to retrieve data and the data is made available by placing it on a system bus. On the other hand, when the FIFO is empty, data is not retrieved until a piece of data has been written.
Previously, when the FIFO is empty, the read operation is inhibited by gating the READ signal with a FIFO empty signal until a write has been performed. In order to ensure that the READ signal has not expired prior to the arrival of the WRITE signal or has a long enough duration after the WRITE signal, the pulse width of the READ signal and its timing in relation to the WRITE signal are required to meet certain predetermined specifications. In general, the need for these specified timing considerations substantially delays the read operation even in excess of an actual memory access operation. Accordingly, it is desirable to provide a fast data access when the FIFO is empty.
In certain circuit applications, a simultaneous write and read memory operation may be desired. Due to the particular structure of the CMOS (Complementary Metal Oxide Semiconductor) technology, a memory cell may not be written and read simultaneously. Accordingly, a need has arisen to advantageously emulate a simultaneous read and write operation to the same memory cell, which allows a read operation to access the data item during the same clock cycle as when it is being written into a FIFO.
The present invention provides for faster memory access from a static memory structure such as a FIFO. The present invention is also applicable to stacks or LIFOs (last in, first out), and is directed to overcoming one or more of the problems as set forth above.